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LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and 8 kB SRAM; USB device
Rev. 3 -- 10 August 2010 Product data sheet
1. General description
The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1311/13/42/43 includes up to 32 kB of flash memory, up to 8 kB of data memory, USB Device (LPC1342/43 only), one Fast-mode Plus I2C-bus interface, one UART, four general purpose timers, and up to 42 general purpose I/O pins.
2. Features and benefits
ARM Cortex-M3 processor, running at frequencies of up to 72 MHz. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). 32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming memory. 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Selectable boot-up: UART or USB (USB on LPC134x only). On LPC134x: USB MSC and HID on-chip drivers. Serial interfaces: USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43 only). UART with fractional baud rate generation, modem, internal FIFO, and RS-485/EIA-485 support. SSP controller with FIFO and multi-protocol capabilities. I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
Other peripherals: Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. Four general purpose counter/timers with a total of four capture inputs and 13 match outputs. Programmable WatchDog Timer (WDT). System tick timer. Serial Wire Debug and Serial Wire Trace port. High-current output driver (20 mA) on one pin. High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus. Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes. Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. Single power supply (2.0 V to 3.6 V). 10-bit ADC with input multiplexing among 8 pins. GPIO pins can be used as edge and level sensitive interrupt sources. Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, or the watchdog clock. Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40 of the functional pins. Brownout detect with four separate thresholds for interrupt and one threshold for forced reset. Power-On Reset (POR). Integrated oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature and voltage range that can optionally be used as a system clock. Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz. System PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. For USB (LPC1342/43), a second, dedicated PLL is provided. Code Read Protection (CRP) with different security levels. Unique device serial number for identification. Available as 48-pin LQFP package and 33-pin HVQFN package.
3. Applications
eMetering Lighting Alarm systems White goods
LPC1311_13_42_43
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Product data sheet
Rev. 3 -- 10 August 2010
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LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
4. Ordering information
Table 1. Ordering information Package Name LPC1311FHN33 HVQFN33 LPC1313FBD48 LQFP48 LPC1313FHN33 HVQFN33 LPC1342FHN33 HVQFN33 LPC1343FBD48 LQFP48 LPC1343FHN33 HVQFN33 Description HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm Version n/a Type number
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 n/a n/a
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 n/a
4.1 Ordering options
Table 2. Ordering options for LPC1311/13/42/43 Flash 8 kB 32 kB 32 kB 16 kB 32 kB 32 kB Total SRAM 4 kB 8 kB 8 kB 4 kB 8 kB 8 kB USB Device Device Device UART RS-485 1 1 1 1 1 1 I2C/ Fast+ 1 1 1 1 1 1 SSP 1 1 1 1 1 1 ADC channels 8 8 8 8 8 8 Pins 33 48 33 33 48 33 Package HVQFN33 LQFP48 HVQFN33 HVQFN33 LQFP48 HVQFN33 Type number LPC1311FHN33 LPC1313FBD48 LPC1313FHN33 LPC1342FHN33 LPC1343FBD48 LPC1343FHN33
LPC1311_13_42_43
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Product data sheet
Rev. 3 -- 10 August 2010
3 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
XTALIN XTALOUT RESET
SWD
USB pins
LPC1311/13/42/43
USB PHY(1)
TEST/DEBUG INTERFACE
IRC WDO
ARM CORTEX-M3
I-code bus D-code bus system bus
USB DEVICE CONTROLLER(1)
POR
CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls slave ROM
CLKOUT
slave
AHB-LITE BUS
slave
SRAM 4/8 kB
GPIO ports PIO0/1/2/3
HIGH-SPEED GPIO
slave
slave AHB TO APB BRIDGE
slave FLASH 8/16/32 kB
RXD TXD DTR, DSR(2), CTS, DCD(2), RI(2), RTS CT32B0_MAT[3:0] CT32B0_CAP0 CT32B1_MAT[3:0] CT32B1_CAP0 CT16B0_MAT[2:0] CT16B0_CAP0 CT16B1_MAT[1:0] CT16B1_CAP0
UART
10-bit ADC
AD[7:0] SCK SSEL MISO MOSI SCL SDA
SSP 32-bit COUNTER/TIMER 0 32-bit COUNTER/TIMER 1 16-bit COUNTER/TIMER 0 16-bit COUNTER/TIMER 1 I2C-BUS
WDT IOCONFIG SYSTEM CONTROL
002aae722
(1) LPC1342/43 only. (2) LQFP48 package only.
Fig 1.
Block diagram
LPC1311_13_42_43
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Product data sheet
Rev. 3 -- 10 August 2010
4 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
6. Pinning information
6.1 Pinning
40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP
39 SWDIO/PIO1_3/AD4/CT32B1_MAT2
46 PIO1_6/RXD/CT32B0_MAT0
47 PIO1_7/TXD/CT32B0_MAT1
45 PIO1_5/RTS/CT32B0_CAP0
42 PIO1_11/AD7
38 PIO2_3/RI
48 PIO3_3
43 PIO3_2
PIO2_6 PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE VSS XTALIN XTALOUT VDD PIO1_8/CT16B1_CAP0
1 2 3 4 5 6 7 8 9
37 PIO3_1 36 PIO3_0 35 R/PIO1_2/AD3/CT32B1_MAT1 34 R/PIO1_1/AD2/CT32B1_MAT0 33 R/PIO1_0/AD1/CT32B1_CAP0 32 R/PIO0_11/AD0/CT32B0_MAT3 31 PIO2_11/SCK 30 PIO1_10/AD6/CT16B1_MAT1 29 SWCLK/PIO0_10/SCK/CT16B0_MAT2 28 PIO0_9/MOSI/CT16B0_MAT1/SWO 27 PIO0_8/MISO/CT16B0_MAT0 26 PIO2_2/DCD 25 PIO2_10 PIO2_9 24
002aae505
44 VDD
LPC1343FBD48
PIO0_2/SSEL/CT16B0_CAP0 10 PIO2_7 11 PIO2_8 12 PIO2_1/DSR 13 PIO0_3/USB_VBUS 14 PIO0_4/SCL 15 PIO0_5/SDA 16 PIO1_9/CT16B1_MAT0 17 PIO2_4 18 USB_DM 19 USB_DP 20 PIO2_5 21 PIO0_6/USB_CONNECT/SCK 22 PIO0_7/CTS 23
Fig 2.
LPC1343 LQFP48 package
LPC1311_13_42_43
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41 VSS
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Product data sheet
Rev. 3 -- 10 August 2010
5 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
PIO1_4/AD5/CT32B1_MAT3/WAKEUP 26
terminal 1 index area PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE XTALIN XTALOUT VDD PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 1 2 3 4 5 6 7 8
32
31
30
29
28
27
25 24 23 22
SWDIO/PIO1_3/AD4/CT32B1_MAT2
PIO1_6/RXD/CT32B0_MAT0
PIO1_7/TXD/CT32B0_MAT1
PIO1_5/RTS/CT32B0_CAP0
PIO1_11/AD7
PIO3_2
VDD
R/PIO1_2/AD3/CT32B1_MAT1 R/PIO1_1/AD2/CT32B1_MAT0 R/PIO1_0/AD1/CT32B1_CAP0 R/PIO0_11/AD0/CT32B0_MAT3 PIO1_10/AD6/CT16B1_MAT1 SWCLK/PIO0_10/SCK/CT16B0_MAT2 PIO0_9/MOSI/CT16B0_MAT1/SWO PIO0_8/MISO/CT16B0_MAT0
LPC1342FHN33 LPC1343FHN33
33 VSS 10 11 12 13 14 15 PIO0_6/USB_CONNECT/SCK 16 PIO0_7/CTS 9
21 20 19 18 17
PIO0_3/USB_VBUS
PIO0_4/SCL
PIO0_5/SDA
PIO1_9/CT16B1_MAT0
USB_DM
USB_DP
002aae516
Transparent top view
Fig 3.
LPC1342/43 HVQFN33 package
LPC1311_13_42_43
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 -- 10 August 2010
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NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP
39 SWDIO/PIO1_3/AD4/CT32B1_MAT2
46 PIO1_6/RXD/CT32B0_MAT0
47 PIO1_7/TXD/CT32B0_MAT1
45 PIO1_5/RTS/CT32B0_CAP0
42 PIO1_11/AD7
38 PIO2_3/RI
48 PIO3_3
43 PIO3_2
PIO2_6 PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 VSS XTALIN XTALOUT VDD PIO1_8/CT16B1_CAP0
1 2 3 4 5 6 7 8 9
37 PIO3_1 36 PIO3_0 35 R/PIO1_2/AD3/CT32B1_MAT1 34 R/PIO1_1/AD2/CT32B1_MAT0 33 R/PIO1_0/AD1/CT32B1_CAP0 32 R/PIO0_11/AD0/CT32B0_MAT3 31 PIO2_11/SCK 30 PIO1_10/AD6/CT16B1_MAT1 29 SWCLK/PIO0_10/SCK/CT16B0_MAT2 28 PIO0_9/MOSI/CT16B0_MAT1/SWO 27 PIO0_8/MISO/CT16B0_MAT0 26 PIO2_2/DCD 25 PIO2_10 PIO2_9 24
002aae513
44 VDD
LPC1313FBD48
PIO0_2/SSEL/CT16B0_CAP0 10 PIO2_7 11 PIO2_8 12 PIO2_1/DSR 13 PIO0_3 14 PIO0_4/SCL 15 PIO0_5/SDA 16 PIO1_9/CT16B1_MAT0 17 PIO3_4 18 PIO2_4 19 PIO2_5 20 PIO3_5 21 PIO0_6/SCK 22 PIO0_7/CTS 23
Fig 4.
LPC1313 LQFP48 package
LPC1311_13_42_43
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41 VSS
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 -- 10 August 2010
7 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
PIO1_4/AD5/CT32B1_MAT3/WAKEUP 26
terminal 1 index area PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 XTALIN XTALOUT VDD PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 1 2 3 4 5 6 7 8
32
31
30
29
28
27
25 24 23 22
SWDIO/PIO1_3/AD4/CT32B1_MAT2
PIO1_6/RXD/CT32B0_MAT0
PIO1_7/TXD/CT32B0_MAT1
PIO1_5/RTS/CT32B0_CAP0
PIO1_11/AD7
PIO3_2
VDD
R/PIO1_2/AD3/CT32B1_MAT1 R/PIO1_1/AD2/CT32B1_MAT0 R/PIO1_0/AD1/CT32B1_CAP0 R/PIO0_11/AD0/CT32B0_MAT3 PIO1_10/AD6/CT16B1_MAT1 SWCLK/PIO0_10/SCK/CT16B0_MAT2 PIO0_9/MOSI/CT16B0_MAT1/SWO PIO0_8/MISO/CT16B0_MAT0
LPC1311FHN33 LPC1313FHN33
33 VSS 10 11 12 13 14 15 PIO0_6/SCK 16 PIO0_7/CTS 9
21 20 19 18 17
PIO0_4/SCL
PIO0_5/SDA
PIO0_3
PIO3_4
PIO1_9/CT16B1_MAT0
PIO3_5
002aae517
Transparent top view
Fig 5.
LPC1311/13 HVQFN33 package
LPC1311_13_42_43
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 -- 10 August 2010
8 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
6.2 Pin description
Table 3. Symbol LPC1313/43 LQFP48 pin description table Pin Start logic input yes Type Reset Description state
[1]
RESET/PIO0_0
3[2]
I
I; PU
RESET -- External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. PIO0_0 -- General purpose digital input/output pin. PIO0_1 -- General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration (USB on LPC1343 only, see description of PIO0_3). CLKOUT -- Clockout pin. CT32B0_MAT2 -- Match output 2 for 32-bit timer 0. USB_FTOGGLE -- USB 1 ms Start-of-Frame signal (LPC1343 only). PIO0_2 -- General purpose digital input/output pin. SSEL -- Slave select for SSP. CT16B0_CAP0 -- Capture input 0 for 16-bit timer 0. PIO0_3 -- General purpose digital input/output pin. LPC1343 only: A LOW level on this pin during reset starts the ISP command handler, a HIGH level starts the USB device enumeration. USB_VBUS -- Monitors the presence of USB bus power (LPC1343 only). PIO0_4 -- General purpose digital input/output pin (open-drain). SCL -- I2C-bus clock input/output (open-drain). High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_5 -- General purpose digital input/output pin (open-drain). SDA -- I2C-bus data input/output (open-drain). High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6 -- General purpose digital input/output pin. USB_CONNECT -- Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature (LPC1343 only). SCK -- Serial clock for SSP. PIO0_7 -- General purpose digital input/output pin (high-current output driver). CTS -- Clear To Send input for UART. PIO0_8 -- General purpose digital input/output pin. MISO -- Master In Slave Out for SSP. CT16B0_MAT0 -- Match output 0 for 16-bit timer 0. PIO0_9 -- General purpose digital input/output pin. MOSI -- Master Out Slave In for SSP. CT16B0_MAT1 -- Match output 1 for 16-bit timer 0. SWO -- Serial wire trace output.
I/O PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGGLE 4[3] yes I/O
I; PU
O O O PIO0_2/SSEL/ CT16B0_CAP0 10[3] yes I/O I/O I PIO0_3/USB_VBUS 14[3] yes I/O
I; PU I; PU
I PIO0_4/SCL 15[4] yes I/O I/O PIO0_5/SDA 16[4] yes I/O I/O PIO0_6/ USB_CONNECT/ SCK 22[3] yes I/O O
I; IA I; IA I; PU -
I/O PIO0_7/CTS 23[3] yes I/O I PIO0_8/MISO/ CT16B0_MAT0 27[3] yes I/O I/O O PIO0_9/MOSI/ CT16B0_MAT1/ SWO 28[3] yes I/O I/O O O
I; PU I; PU I; PU -
LPC1311_13_42_43
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 -- 10 August 2010
9 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
Table 3. Symbol
LPC1313/43 LQFP48 pin description table ...continued Pin Start logic input Type Reset Description state
[1]
SWCLK/PIO0_10/ 29[3] yes SCK/CT16B0_MAT2
I I/O I/OO O
I; PU I; PU I; PU I; PU I; PU I; PU I; PU -
SWCLK -- Serial wire clock. PIO0_10 -- General purpose digital input/output pin. SCK -- Serial clock for SSP. CT16B0_MAT2 -- Match output 2 for 16-bit timer 0. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO0_11 -- General purpose digital input/output pin. AD0 -- A/D converter, input 0. CT32B0_MAT3 -- Match output 3 for 32-bit timer 0. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_0 -- General purpose digital input/output pin. AD1 -- A/D converter, input 1. CT32B1_CAP0 -- Capture input 0 for 32-bit timer 1. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_1 -- General purpose digital input/output pin. AD2 -- A/D converter, input 2. CT32B1_MAT0 -- Match output 0 for 32-bit timer 1. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_2 -- General purpose digital input/output pin. AD3 -- A/D converter, input 3. CT32B1_MAT1 -- Match output 1 for 32-bit timer 1. SWDIO -- Serial wire debug input/output. PIO1_3 -- General purpose digital input/output pin. AD4 -- A/D converter, input 4. CT32B1_MAT2 -- Match output 2 for 32-bit timer 1. PIO1_4 -- General purpose digital input/output pin. AD5 -- A/D converter, input 5. CT32B1_MAT3 -- Match output 3 for 32-bit timer 1. WAKEUP -- Deep power-down mode wake-up pin. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. PIO1_5 -- General purpose digital input/output pin. RTS -- Request To Send output for UART. CT32B0_CAP0 -- Capture input 0 for 32-bit timer 0. PIO1_6 -- General purpose digital input/output pin. RXD -- Receiver input for UART. CT32B0_MAT0 -- Match output 0 for 32-bit timer 0.
(c) NXP B.V. 2010. All rights reserved.
R/PIO0_11/ AD0/CT32B0_MAT3
32[5]
yes
I/O I O
R/PIO1_0/ AD1/CT32B1_CAP0
33[5]
yes
I/O I I
R/PIO1_1/ 34[5] yes AD2/CT32B1_MAT0
I/O I O
R/PIO1_2/ AD3/CT32B1_MAT1
35[5]
yes
I/O I O
SWDIO/PIO1_3/ AD4/ CT32B1_MAT2
39[5]
yes
I/O I/O I O
PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP
40[5]
yes
I/O I O I
PIO1_5/RTS/ CT32B0_CAP0
45[3] yes
I/O O I
I; PU I; PU -
PIO1_6/RXD/ CT32B0_MAT0
46[3] yes
I/O I O
LPC1311_13_42_43
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Product data sheet
Rev. 3 -- 10 August 2010
10 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
Table 3. Symbol
LPC1313/43 LQFP48 pin description table ...continued Pin Start logic input Type Reset Description state
[1]
PIO1_7/TXD/ CT32B0_MAT1
47[3] yes
I/O O O
I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU F F
PIO1_7 -- General purpose digital input/output pin. TXD -- Transmitter output for UART. CT32B0_MAT1 -- Match output 1 for 32-bit timer 0. PIO1_8 -- General purpose digital input/output pin. CT16B1_CAP0 -- Capture input 0 for 16-bit timer 1. PIO1_9 -- General purpose digital input/output pin. CT16B1_MAT0 -- Match output 0 for 16-bit timer 1. PIO1_10 -- General purpose digital input/output pin. AD6 -- A/D converter, input 6. CT16B1_MAT1 -- Match output 1 for 16-bit timer 1. PIO1_11 -- General purpose digital input/output pin. AD7 -- A/D converter, input 7. PIO2_0 -- General purpose digital input/output pin. DTR -- Data Terminal Ready output for UART. PIO2_1 -- General purpose digital input/output pin. DSR -- Data Set Ready input for UART. PIO2_2 -- General purpose digital input/output pin. DCD -- Data Carrier Detect input for UART. PIO2_3 -- General purpose digital input/output pin. RI -- Ring Indicator input for UART. PIO2_4 -- General purpose digital input/output pin (LPC1343 only). PIO2_4 -- General purpose digital input/output pin (LPC1313 only). PIO2_5 -- General purpose digital input/output pin (LPC1343 only). PIO2_5 -- General purpose digital input/output pin (LPC1313 only). PIO2_6 -- General purpose digital input/output pin. PIO2_7 -- General purpose digital input/output pin. PIO2_8 -- General purpose digital input/output pin. PIO2_9 -- General purpose digital input/output pin. PIO2_10 -- General purpose digital input/output pin. PIO2_11 -- General purpose digital input/output pin. SCK -- Serial clock for SSP. PIO3_0 -- General purpose digital input/output pin. PIO3_1 -- General purpose digital input/output pin. PIO3_2 -- General purpose digital input/output pin. PIO3_3 -- General purpose digital input/output pin. PIO3_4 -- General purpose digital input/output pin (LPC1313 only). PIO3_5 -- General purpose digital input/output pin (LPC1313 only). USB_DM -- USB bidirectional D- line (LPC1343 only). USB_DP -- USB bidirectional D+ line (LPC1343 only).
(c) NXP B.V. 2010. All rights reserved.
PIO1_8/CT16B1_C AP0 PIO1_9/CT16B1_M AT0 PIO1_10/AD6/ CT16B1_MAT1
9[3] 17[3] 30[5]
yes yes yes
I/O I I/O O I/O I O
PIO1_11/AD7 PIO2_0/DTR PIO2_1/DSR PIO2_2/DCD PIO2_3/RI PIO2_4 PIO2_4 PIO2_5 PIO2_5 PIO2_6 PIO2_7 PIO2_8 PIO2_9 PIO2_10 PIO2_11/SCK PIO3_0 PIO3_1 PIO3_2 PIO3_3 PIO3_4 PIO3_5 USB_DM USB_DP
LPC1311_13_42_43
42[5] yes 2[3] yes
I/O I I/O O I/O I I/O I I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
13[3] yes 26[3] yes
38[3] yes 18[3] 19[3] 20[3] 1[3] 11[3] 24[3] 25[3] 31[3] 36[3] 37[3] 43[3] 18[3] 21[3] 19[6] yes yes yes yes yes yes yes yes yes yes yes no no no
21[3] yes
12[3] yes
48[3] yes
20[6] no
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Product data sheet
Rev. 3 -- 10 August 2010
11 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
Table 3. Symbol
LPC1313/43 LQFP48 pin description table ...continued Pin Start logic input Type Reset Description state
[1]
VDD XTALIN XTALOUT VSS
8; 44 6[7] 7[7] 5; 41
I I O I
-
3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. Output from the oscillator amplifier. Ground.
[1] [2] [3] [4] [5] [6] [7]
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. See Figure 31 for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 30). I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 30). Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
Table 4. Symbol
LPC1311/13/42/43 HVQFN33 pin description table Pin Start Type Reset Description logic state [1] input yes I I; PU RESET -- External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. PIO0_0 -- General purpose digital input/output pin. PIO0_1 -- General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration (USB on LPC1342/43 only, see description of PIO0_3). CLKOUT -- Clock out pin. CT32B0_MAT2 -- Match output 2 for 32-bit timer 0. USB_FTOGGLE -- USB 1 ms Start-of-Frame signal (LPC1342/43 only). PIO0_2 -- General purpose digital input/output pin. SSEL -- Slave select for SSP. CT16B0_CAP0 -- Capture input 0 for 16-bit timer 0. PIO0_3 -- General purpose digital input/output pin. LPC1342/43 only: A LOW level on this pin during reset starts the ISP command handler, a HIGH level starts the USB device enumeration. USB_VBUS -- Monitors the presence of USB bus power (LPC1342/43 only). PIO0_4 -- General purpose digital input/output pin (open-drain). SCL -- I2C-bus clock input/output (open-drain). High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register.
(c) NXP B.V. 2010. All rights reserved.
RESET/PIO0_0
2[2]
I/O PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGGLE 3[3] yes I/O
I; PU
O O O PIO0_2/SSEL/ CT16B0_CAP0 8[3] yes I/O I/O I PIO0_3/ USB_VBUS 9[3] yes I/O
I; PU I; PU
I PIO0_4/SCL 10[4] yes I/O I/O
LPC1311_13_42_43
I; IA -
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Table 4. Symbol
LPC1311/13/42/43 HVQFN33 pin description table ...continued Pin Start Type Reset Description logic state [1] input I/O I/O I; IA I; PU PIO0_5 -- General purpose digital input/output pin (open-drain). SDA -- I2C-bus data input/output (open-drain). High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6 -- General purpose digital input/output pin. USB_CONNECT -- Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature (LPC1342/43 only). SCK -- Serial clock for SSP. PIO0_7 -- General purpose digital input/output pin (high-current output driver). CTS -- Clear To Send input for UART. PIO0_8 -- General purpose digital input/output pin. MISO -- Master In Slave Out for SSP. CT16B0_MAT0 -- Match output 0 for 16-bit timer 0. PIO0_9 -- General purpose digital input/output pin. MOSI -- Master Out Slave In for SSP. CT16B0_MAT1 -- Match output 1 for 16-bit timer 0. SWO -- Serial wire trace output. SWCLK -- Serial wire clock. PIO0_10 -- General purpose digital input/output pin. SCK -- Serial clock for SSP. CT16B0_MAT2 -- Match output 2 for 16-bit timer 0. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO0_11 -- General purpose digital input/output pin. AD0 -- A/D converter, input 0. CT32B0_MAT3 -- Match output 3 for 32-bit timer 0. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_0 -- General purpose digital input/output pin. AD1 -- A/D converter, input 1. CT32B1_CAP0 -- Capture input 0 for 32-bit timer 1. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_1 -- General purpose digital input/output pin. AD2 -- A/D converter, input 2. CT32B1_MAT0 -- Match output 0 for 32-bit timer 1.
PIO0_5/SDA
11[4] yes
PIO0_6/ USB_CONNECT/ SCK
15[3] yes
I/O O
I/O PIO0_7/CTS 16[3] yes I/O I PIO0_8/MISO/ CT16B0_MAT0 17[3] yes I/O I/O O PIO0_9/MOSI/ CT16B0_MAT1/ SWO 18[3] yes I/O I/O O O SWCLK/PIO0_10/ SCK/ CT16B0_MAT2 19[3] yes I I/O O O R/PIO0_11/AD0/ CT32B0_MAT3 21[5] yes I/O I O R/PIO1_0/AD1/ CT32B1_CAP0 22[5] yes I/O I I R/PIO1_1/AD2/ CT32B1_MAT0 23[5] yes I/O I O
I; PU I; PU I; PU I; PU I; PU I; PU I; PU -
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Table 4. Symbol
LPC1311/13/42/43 HVQFN33 pin description table ...continued Pin Start Type Reset Description logic state [1] input I/O I O I; PU I; PU I; PU R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_2 -- General purpose digital input/output pin. AD3 -- A/D converter, input 3. CT32B1_MAT1 -- Match output 1 for 32-bit timer 1. SWDIO -- Serial wire debug input/output. PIO1_3 -- General purpose digital input/output pin. AD4 -- A/D converter, input 4. CT32B1_MAT2 -- Match output 2 for 32-bit timer 1. PIO1_4 -- General purpose digital input/output pin. AD5 -- A/D converter, input 5. CT32B1_MAT3 -- Match output 3 for 32-bit timer 1. WAKEUP -- Deep power-down mode wake-up pin. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. PIO1_5 -- General purpose digital input/output pin. RTS -- Request To Send output for UART. CT32B0_CAP0 -- Capture input 0 for 32-bit timer 0. PIO1_6 -- General purpose digital input/output pin. RXD -- Receiver input for UART. CT32B0_MAT0 -- Match output 0 for 32-bit timer 0. PIO1_7 -- General purpose digital input/output pin. TXD -- Transmitter output for UART. CT32B0_MAT1 -- Match output 1 for 32-bit timer 0. PIO1_8 -- General purpose digital input/output pin. CT16B1_CAP0 -- Capture input 0 for 16-bit timer 1. PIO1_9 -- General purpose digital input/output pin. CT16B1_MAT0 -- Match output 0 for 16-bit timer 1. PIO1_10 -- General purpose digital input/output pin. AD6 -- A/D converter, input 6. CT16B1_MAT1 -- Match output 1 for 16-bit timer 1. PIO1_11 -- General purpose digital input/output pin. AD7 -- A/D converter, input 7. PIO2_0 -- General purpose digital input/output pin. DTR -- Data Terminal Ready output for UART. PIO3_2 -- General purpose digital input/output pin. PIO3_4 -- General purpose digital input/output pin (LPC1311/13 only). PIO3_5 -- General purpose digital input/output pin (LPC1311/13 only). USB_DM -- USB bidirectional D- line (LPC1342/43 only). USB_DP -- USB bidirectional D+ line (LPC1342/43 only).
(c) NXP B.V. 2010. All rights reserved.
R/PIO1_2/AD3/ CT32B1_MAT1
24[5] yes
SWDIO/PIO1_3/ AD4/ CT32B1_MAT2
25[5]
yes
I/O I/O I O
PIO1_4/AD5/ CT32B1_MAT3/WA KEUP
26[5]
yes
I/O I O I
PIO1_5/RTS/ CT32B0_CAP0
30[3] yes
I/O O I
I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU F F
PIO1_6/RXD/ CT32B0_MAT0
31[3] yes
I/O I O
PIO1_7/TXD/ CT32B0_MAT1
32[3]
yes
I/O O O
PIO1_8/ CT16B1_CAP0 PIO1_9/ CT16B1_MAT0 PIO1_10/AD6/ CT16B1_MAT1
7[3]
yes
I/O I I/O O I/O I O
12[3] yes 20[5] yes
PIO1_11/AD7 PIO2_0/DTR PIO3_2 PIO3_4 PIO3_5 USB_DM USB_DP
LPC1311_13_42_43
27[5] 1[3] 28[3] 13[3] 14[3] 14[6]
yes yes yes no no no
I/O I I/O O I/O I/O I/O I/O I/O
13[6] no
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Table 4. Symbol
LPC1311/13/42/43 HVQFN33 pin description table ...continued Pin Start Type Reset Description logic state [1] input I I O 3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. Output from the oscillator amplifier. Thermal pad. Connect to ground.
VDD XTALIN XTALOUT VSS
[1] [2] [3] [4] [5] [6] [7]
6; 29 4[7] 5[7] 33
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled. F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. See Figure 31 for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 30). I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 30). Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
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7. Functional description
7.1 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.
7.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual which is available on the official ARM website.
7.3 On-chip flash program memory
The LPC1311/13/42/43 contain 32 kB (LPC1313 and LPC1343), 16 kB (LPC1342), or 8 kB (LPC1311) of on-chip flash memory.
7.4 On-chip SRAM
The LPC1311/13/42/43 contain a total of 8 kB (LPC1343 and LPC1313) or 4 kB (LPC1342 and LPC1311) on-chip static RAM memory.
7.5 Memory map
The LPC134x incorporates several distinct memory regions, shown in the following figures. Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.
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4 GB
LPC1311/13/42/43
0xFFFF FFFF reserved 0xE010 0000 private peripheral bus reserved 0x5020 0000 AHB peripherals 0x5000 0000 0xE000 0000 12-15 8-11 4-7 0-3 reserved
AHB peripherals
0x5020 0000
16 - 127 reserved 0x5004 0000 GPIO PIO3 GPIO PIO2 GPIO PIO1 GPIO PIO0 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000
APB peripherals
0x4008 0000
0x4008 0000 1 GB APB peripherals reserved 0x2400 0000 AHB SRAM bit-band alias addressing 0x2200 0000 0x4000 0000 18 17 16 15 14 0x2000 0000
19 - 31 reserved 0x4004 C000 system control IOCONFIG SSP flash controller PMU 10 - 13 reserved 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000
reserved 0.5 GB reserved 0x1FFF 4000 16 kB boot ROM 0x1FFF 0000
0x4002 8000 9 8 7 reserved USB (LPC1342/43 only) ADC 32-bit counter/timer 1 32-bit counter/timer 0 16-bit counter/timer 1 16-bit counter/timer 0 UART WDT I2C-bus 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000
reserved 0x1000 2000 I-code/D-code memory space 8 kB SRAM (LPC1313/1343) 4 kB SRAM (LPC1311/1342) 0x1000 1000 0x1000 0000
6 5 4 3 2 1 0 0x0000 8000
reserved
32 kB on-chip flash (LPC1313/43) 16 kB on-chip flash (LPC1342) 0 GB 8 kB on-chip flash (LPC1311)
0x0000 4000 0x0000 2000 0x0000 0000
+ 256 words active interrupt vectors
0x0000 0400 0x0000 0000
002aae723
Fig 6.
LPC1311/13/42/43 memory map
7.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.
7.6.1 Features
* Controls system exceptions and peripheral interrupts. * On the LPC1311/13/42/43, the NVIC supports 16 vectored interrupts. In addition, up
to 40 of the individual GPIO inputs are NVIC-vector capable.
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* 8 programmable interrupt priority levels, with hardware priority level masking * Relocatable vector table. * Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both.
7.7 IOCONFIG block
The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.
7.8 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC1311/13/42/43 use accelerated GPIO functions:
* GPIO block is a dedicated AHB peripheral so that the fastest possible I/O timing can
be achieved.
* Entire port value can be written in one instruction.
Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.8.1 Features
* Bit level port registers allow a single instruction to set or clear any number of bits in
one write operation.
* Direction control of individual bits. * All I/O default to inputs with pull-up resistors enabled after reset with the exception of
the I2C-bus pins PIO0_4 and PIO0_5.
* Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG
block for each GPIO pin.
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7.9 USB interface (LPC1342/43 only)
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The LPC1342/43 USB interface is a device controller with on-chip PHY for device functions.
7.9.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. 7.9.1.1 Features
* Dedicated USB PLL available. * Fully compliant with USB 2.0 specification (full speed). * Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per
endpoint (see Table 5).
* Supports Control, Bulk, Isochronous, and Interrupt endpoints. * Supports SoftConnect feature. * Double buffer implementation for Bulk and Isochronous endpoints.
Table 5. Logical endpoint 0 0 1 1 2 2 3 3 4 4 USB device endpoint configuration Physical endpoint 0 1 2 3 4 5 6 7 8 9 Endpoint type Control Control Interrupt/Bulk Interrupt/Bulk Interrupt/Bulk Interrupt/Bulk Interrupt/Bulk Interrupt/Bulk Isochronous Isochronous Direction out in out in out in out in out in Packet size (byte) 64 64 64 64 64 64 64 64 512 512 Double buffer no no no no no no yes yes yes yes
7.10 UART
The LPC1311/13/42/43 contains one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode.
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The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.10.1 Features
* * * * *
Maximum UART data bit rate of 4.5 MBit/s. 16-byte receive and transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. mechanism that enables software flow control implementation.
* Fractional divider for baud rate control, auto baud capabilities and FIFO control * Support for RS-485/9-bit mode. * Support for modem control. 7.11 SSP serial I/O controller
The LPC1311/13/42/43 contain one SSP controller. The SSP controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.
7.11.1 Features
* Maximum SSP speed of 36 Mbit/s (master) or 6 Mbit/s (slave) * Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
* * * *
Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame
7.12 I2C-bus serial I/O controller
The LPC1311/13/42/43 contain one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it.
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7.12.1 Features
* The I2C-bus interface is a standard I2C-bus compliant interface with true open-drain
pins. The I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
* * * * *
Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus.
* Serial clock synchronization allows devices with different bit rates to communicate via * Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
* The I2C-bus can be used for test and diagnostic purposes. * The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.13 10-bit ADC
The LPC1311/13/42/43 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels.
7.13.1 Features
* * * * * * * *
10-bit successive approximation ADC. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 V to VDD. 10-bit conversion time 2.44 s (up to 400 kSamples/s). Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or timer match signal. Individual result registers for each ADC channel to reduce interrupt overhead.
7.14 General purpose external event counter/timers
The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.
7.14.1 Features
* A 32-bit/16-bit counter/timer with a programmable 32-bit/16-bit prescaler. * Counter or timer operation. * One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
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* Four match registers per timer that allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Up to four external outputs corresponding to match registers, with the following
capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match.
7.15 System tick timer
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval, normally set to 10 ms.
7.16 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a selectable time period. When enabled, the watchdog will generate a system reset if the user program fails to `feed' (or reload) the watchdog within a predetermined amount of time.
7.16.1 Features
* Internally resets chip if not periodically reloaded. * Debug mode. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
* * * *
Incorrect/incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) x 256 x 4) to (Tcy(WDCLK) x 232 x 4) in multiples of Tcy(WDCLK) x 4. (IRC), the watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability.
* The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
7.17 Clocking and power control
7.17.1 Integrated oscillators
The LPC1311/13/42/43 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application.
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Following reset, the LPC1311/13/42/43 will operate from the internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 7 for an overview of the LPC1311/13/42/43 clock generation.
SYSTEM CLOCK DIVIDER
system clock
AHB clock 0 (system) AHB clock 1 (ROM) AHBCLKCTRL (AHB clock enable)
14
AHB clocks 2 to 15 (memories and peripherals) AHB clock 16 (IOCONFIG)
AHBCLKCTRL
AHBCLKCTRL SSP PERIPHERAL CLOCK DIVIDER main clock UART PERIPHERAL CLOCK DIVIDER ARM TRACE CLOCK DIVIDER SYSTICK TIMER CLOCK DIVIDER SYSTEM PLL system oscillator SYSPLLCLKSEL (system PLL clock select) IRC oscillator WDT CLOCK DIVIDER watchdog oscillator WDTUEN (WDT clock update enable) system oscillator USB PLL USB 48 MHz CLOCK DIVIDER WDT UART SSP
IRC oscillator
watchdog oscillator
MAINCLKSEL (main clock select) IRC oscillator
ARM trace clock SYSTICK timer
USB
USBPLLCLKSEL (USB clock select)
USBUEN (USB clock update enable) IRC oscillator system oscillator watchdog oscillator CLKOUT PIN CLOCK DIVIDER
CLKOUT pin
CLKOUTUEN (CLKOUT update enable)
002aae859
The USB clock is available on LPC1342/43 only.
Fig 7.
LPC1311/13/42/43 clocking generation block diagram
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7.17.1.1
Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of the other available clock sources.
7.17.1.2
System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC134x, the system oscillator must be used to provide the clock source to USB. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.
7.17.1.3
Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is 40 % (see also Table 14).
7.17.2 System PLL and USB PLL
The LPC134x contain a system PLL and a dedicated PLL for generating the 48 MHz USB clock. The LPC131x contain the system PLL only. The system and USB PLLs are identical. The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s.
7.17.3 Clock output
The LPC1311/13/42/43 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin.
7.17.4 Wake-up process
The LPC1311/13/42/43 begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.
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7.17.5 Power control
The LPC1311/13/42/43 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.17.5.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.17.5.2 Deep-sleep mode In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down. As an exception, the user has the option to keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows for additional power savings. Up to 40 pins total can serve as external wake-up pins to the start logic to wake up the chip from Deep-sleep mode (see Section 7.18.1). Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source should be switched to IRC before entering Deep-sleep mode, because the IRC can be switched on and off glitch-free. 7.17.5.3 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC1311/13/42/43 can wake up from Deep power-down mode via the WAKEUP pin.
7.18 System control
7.18.1 Start logic
The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in Table 3 and Table 4 as input to the start logic has an individual interrupt in the NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down. The start logic must be configured in the system configuration block and in the NVIC before being used.
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7.18.2 Reset
Reset has four sources on the LPC1311/13/42/43: the RESET pin, the Watchdog reset, power-on reset (POR), and the Brown-Out Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. When the internal reset is removed, the processor begins executing at address 0, which is initially the reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.
7.18.3 Brownout detection
The LPC1311/13/42/43 includes four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. An additional threshold level can be selected to cause a forced reset of the chip.
7.18.4 Code security (Code Read Protection - CRP)
This feature of the LPC1311/13/42/43 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. In-Application Programming (IAP) commands are not affected by the CRP. In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP (NO_ISP mode). For details see the LPC13xx user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. 2. CRP2 disables access to chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too. It is up to the user's application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.
CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.
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7.18.5 Boot loader
The boot loader controls initial operation after reset and also provides the means to program the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. The boot loader code is executed every time the part is reset or powered up. The loader can either execute the ISP command handler or the user application code, or, on the LPC134x, it can program the flash image via an attached MSC device through USB (Windows operating system only). A LOW level during reset applied to the PIO0_1 pin is considered as an external hardware request to start the ISP command handler or the USB device enumeration. The state of PIO0_3 determines whether the UART or USB interface will be used (LPC134x only).
7.18.6 APB interface
The APB peripherals are located on one APB bus.
7.18.7 AHB-Lite
The AHB-Lite connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main static RAM, and the boot ROM.
7.18.8 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs serve as external interrupts (see Section 7.18.1).
7.18.9 Memory mapping control
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 256 word boundary.
7.19 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M3. Serial wire debug is supported.
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8. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD VI Parameter supply voltage (core and external rail) input voltage 5 V tolerant I/O pins; only valid when the VDD supply voltage is present per supply pin per ground pin -(0.5VDD) < VI < (1.5VDD); Tj < 125 C Tstg Tj(max) Ptot(pack) VESD
[1]
[4] [2]
Conditions
Min 2.0 -0.5
Max 3.6 +5.5
Unit V V
IDD ISS Ilatch
supply current ground current I/O latch-up current storage temperature maximum junction temperature total power dissipation (per package) electrostatic discharge voltage
[3] [3]
-65 -
100 100 100 +150 150 1.5 +6500
mA mA mA C C W V
based on package heat transfer, not device power consumption human body model; all pins
[5]
-6500
The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
[2] [3] [4] [5]
Including voltage on outputs in 3-state mode. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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9. Static characteristics
Table 7. Static characteristics Tamb = -40 C to +85 C, unless otherwise specified. Symbol Parameter VDD IDD supply voltage (core and external rail) supply current Active mode; VDD = 3.3 V; Tamb = 25 C; code Conditions Min 2.0 Typ[1] 3.3 Max 3.6 Unit V
while(1){}
executed from flash; system clock = 12 MHz system clock = 72 MHz Sleep mode; VDD = 3.3 V; Tamb = 25 C; system clock = 12 MHz Deep-sleep mode; VDD = 3.3 V; Tamb = 25 C Deep power-down mode; VDD = 3.3 V; Tamb = 25 C IIL IIH IOZ VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current IOH = -4 mA IOL = 4 mA VOH = VDD - 0.4 V VOL = 0.4 V
[13] [3][8][6] [2][3][4] [5][6] [3][4][5] [7][6] [2][3][4] [5][6]
-
4 17 2
-
mA mA mA
-
30 220
-
A nA
[9]
Standard port pins and RESET pin; see Figure 16, Figure 17, Figure 18, Figure 19 [10][11] [12]
0.5 0.5 0.5 -
10 10 10 5.0 VDD 0.3VDD 0.4 -45 50
nA nA nA V V V V V V V mA mA mA mA
VI = VDD; on-chip pull-down resistor disabled VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled pin configured to provide a digital function output active
0 0 0.7VDD 0.4
VDD - 0.4 -4 4 -
HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current VOL = VDD
[13]
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Table 7. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Symbol Parameter Ipd Ipu pull-down current pull-up current Conditions VI = 5 V VI = 0 V VDD < VI < 5 V High-drive output pin (PIO0_7); see Figure 14 and Figure 16 IIL IIH IOZ VI VO VIH VIL Vhys VOH VOL IOH IOL Ipd Ipu LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current pull-down current pull-up current IOH = -20 mA IOL = 4 mA VOH = VDD - 0.4 V; VDD 2.5 V VOL = 0.4 V VI = 5 V VI = 0 V VDD < VI < 5 V I2C-bus pins (PIO0_4 and PIO0_5); see Figure 15 VIH VIL Vhys VOL ILI HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS = 20 mA VI = VDD VI = 5 V Oscillator pins Vi(xtal) Vo(xtal) IOZ crystal input voltage crystal output voltage OFF-state output current 0 V < VI < 3.3 V -0.5 -0.5 +1.8 +1.8 +1.95 +1.95 10 V V A
[14]
Min 10 -15 0 [10][11] [12]
Typ[1] 50 -50 0 0.5 0.5 0.5 -
Max 150 -85 0 10 10 10 5.0 VDD 0.3VDD 0.4 150 -85 0 0.3VDD 0.4 4 22
Unit A A A nA nA nA V V V V V V V mA mA A A A V V V V A A
VI = VDD; on-chip pull-down resistor disabled VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled pin configured to provide a digital function output active
0 0 0.7VDD 0.4
VDD - 0.4 20 4 10 -15 0 0.7VDD 50 -50 0 0.5VDD 2 10
USB pins (LPC1342/43 only)
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Table 7. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Symbol Parameter VBUS VDI VCM Vth(rs)se bus supply voltage differential input sensitivity voltage differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage HIGH-level output voltage for low-/full-speed; RL of 1.5 k to 3.6 V driven; for low-/full-speed; RL of 15 k to GND
[15]
Conditions |(D+) - (D-)| includes VDI range
Min 0.2 0.8 0.8
Typ[1] -
Max 5.25 2.5 2.0
Unit V V V V
VOL VOH Ctrans ZDRV
2.8 36
-
0.18 3.5 20 44.1
V V pF
transceiver capacitance pin to GND driver output with 33 series resistor; steady state impedance for driver drive which is not high-speed capable
[1] [2] [3] [4] [5] [6] [7] [8] [9]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. IRC enabled; system oscillator disabled; system PLL disabled. IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. BOD disabled. All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART, SSP, trace clock, and SysTick timer disabled in the syscon block. For LPC134x: USB_DP and USB_DM pulled LOW externally. IRC disabled; system oscillator enabled; system PLL enabled. All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF. WAKEUP pin pulled HIGH externally.
[10] Including voltage on outputs in 3-state mode. [11] VDD supply voltage must be present. [12] 3-state outputs go into 3-state mode in Deep power-down mode. [13] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [14] To VSS. [15] Includes external resistors of 33 1 % on USB_DP and USB_DM.
Table 8. ADC static characteristics Tamb = -40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol VIA Cia ED EL(adj) EO EG Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error
[1][2] [3] [4] [5]
Conditions
Min 0 -
Typ -
Max VDD 1 1 1.5 3.5 0.6
Unit V pF LSB LSB LSB %
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Table 8. ADC static characteristics ...continued Tamb = -40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol ET Rvsi Ri
[1] [2] [3] [4] [5] [6] [7] [8]
Parameter absolute error voltage source interface resistance input resistance
Conditions
[6]
Min [7][8]
Typ -
Max 4 40 2.5
Unit LSB k M
-
The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 8. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 8. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 8. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 8. Tamb = 25 C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF. Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs x Cia).
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offset error EO 1023
gain error EG
1022
1021
1020
1019
1018
(2)
7 code out 6
(1)
5
(5)
4
(4)
3
(3)
2
1
1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024
0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal)
1 LSB =
VDD - VSS 1024
002aaf426
(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.
Fig 8.
ADC characteristics
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9.1 BOD static characteristics
Table 9. BOD static characteristics[1] Tamb = 25 C. Symbol Vth Parameter threshold voltage Conditions interrupt level 0 assertion de-assertion interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 0 assertion de-assertion
[1]
Min -
Typ 1.69 1.84 2.29 2.44 2.59 2.74 2.87 2.98 1.49 1.64
Max -
Unit V V V V V V V V V V
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx user manual.
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC13xx user manual):
* Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. * Configure GPIO pins as outputs using the GPIOnDIR registers. * Write 0 to all GPIOnDATA registers to drive the outputs LOW.
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18 IDD (mA) 15 72 MHz
002aae993
12
48 MHz
9
36 MHz
24 MHz 6 12 MHz 3 2.0 2.4 2.8 3.2 VDD (V) 3.6
Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC134x).
Fig 9.
Typical supply current versus regulator supply voltage VDD in active mode
18 IDD (mA) 15 72 MHz
002aae994
12
48 MHz
9
36 MHz
24 MHz 6 12 MHz 3 -40 -15 10 35 60 85 temperature (C)
Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC134x).
Fig 10. Typical supply current versus temperature in Active mode
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10 IDD (mA) 8 48 MHz 6 36 MHz 4 24 MHz 12 MHz 2 72 MHz
002aae995
0 -40
-15
10
35
60 85 temperature (C)
Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC134x).
Fig 11. Typical supply current versus temperature in Sleep mode
80 IDD (A) 60 VDD = 3.6 V 3.3 V 2.0 V
002aae998
40
20
0 -40
-15
10
35
60 85 temperature (C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF; USB_DP and USB_DM pulled LOW externally (LPC134x).
Fig 12. Typical supply current versus temperature in Deep-sleep mode (analog blocks disabled)
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1.2 IDD (A) 0.6 VDD = 3.6 V 3.3 V 2.0 V 0.4
002aae996
0 -40
-15
10
35
60 85 temperature (C)
Fig 13. Typical supply current versus temperature in Deep power-down mode
9.3 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG or PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, and 72 MHz.
Table 10. Peripheral IRC System oscillator at 12 MHz Watchdog oscillator at 500 kHz/2 BOD Main or USB PLL ADC CLKOUT CT16B0 CT16B1 CT32B0 CT32B1 Power consumption for individual analog and digital blocks Typical supply current in mA n/a 0.23 0.23 0.002 12 MHz 48 MHz 72 MHz System oscillator running; PLL off; independent of main clock frequency. IRC running; PLL off; independent of main clock frequency. System oscillator running; PLL off; independent of main clock frequency. Independent of main clock frequency. Notes
0.045 -
0.26 0.07 0.14 0.01 0.01 0.01 0.01
0.34 0.25 0.56 0.05 0.04 0.05 0.04
0.48 0.37 0.82 0.08 0.06 0.07 0.06
Main clock divided by 4 in the CLKOUTDIV register.
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Table 10. Peripheral GPIO
Power consumption for individual analog and digital blocks ...continued Typical supply current in mA n/a 12 MHz 0.21 48 MHz 0.80 72 MHz 1.17 GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. Notes
IOCONFIG I2C ROM SSP UART WDT USB USB
-
0.00 0.03 0.04 0.11 0.20 0.01 1.84
0.02 0.12 0.15 0.41 0.76 0.05 3.91 4.19
0.02 0.17 0.22 0.60 1.11 0.08 5.71 Main clock selected as clock source for the WDT. Main clock selected as clock source for the USB. USB_DP and USB_DM pulled LOW externally. Dedicated USB PLL selected as cock source for the USB. USB_DP and USB_DM pulled LOW externally.
9.4 Electrical pin characteristics
3.6 VOH (V) 3.2 T = 85 C 25 C -40 C
002aae990
2.8
2.4
2 0 10 20 30 40 50 IOH (mA) 60
Conditions: VDD = 3.3 V; on pin PIO0_7.
Fig 14. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH.
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60 IOL (mA) 40 T = 85 C 25 C -40 C
002aaf019
20
0 0 0.2 0.4 VOL (V) 0.6
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.
Fig 15. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL
15 IOL (mA) 10 T = 85 C 25 C -40 C
002aae991
5
0 0 0.2 0.4 VOL (V) 0.6
Conditions: VDD = 3.3 V; standard port pins and PIO0_7.
Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL
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3.6 VOH (V) 3.2
002aae992
T = 85 C 25 C -40 C
2.8
2.4
2 0 8 16 IOH (mA) 24
Conditions: VDD = 3.3 V; standard port pins.
Fig 17. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH
10 Ipu (A) -10
002aae988
-30 T = 85 C 25 C -40 C
-50
-70
0
1
2
3
4 VI (V)
5
Conditions: VDD = 3.3 V; standard port pins.
Fig 18. Typical pull-up current Ipu versus input voltage Vi
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80 Ipd (A) 60 T = 85 C 25 C -40 C
002aae989
40
20
0 0 1 2 3 4 VI (V) 5
Conditions: VDD = 3.3 V; standard port pins.
Fig 19. Typical pull-down current Ipd versus input voltage Vi
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10. Dynamic characteristics
10.1 Flash memory
Table 11. Flash characteristics Tamb = -40 C to +85 C, unless otherwise specified. Symbol Nendu tret ter tprog
[1] [2]
Parameter endurance retention time erase time programming time
Conditions
[1]
Min 10000 10 20 95
[2]
Typ 100 1
Max 105 1.05
Unit cycles years years ms ms
powered unpowered sector or multiple consecutive sectors
0.95
Number of program/erase cycles. Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.
10.2 External clock
Table 12. Dynamic characteristic: external clock Tamb = -40 C to +85 C; VDD over specified ranges.[1] Symbol fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL
[1] [2]
Parameter oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time
Conditions
Min 1 40 Tcy(clk) x 0.4 Tcy(clk) x 0.4 -
Typ[2] -
Max 25 1000 5 5
Unit MHz ns ns ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 20. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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10.3 Internal oscillators
Table 13. Dynamic characteristics: IRC Tamb = -40 C to +85 C; 2.7 V VDD 3.6 V[1]. Symbol fosc(RC)
[1] [2]
Parameter internal RC oscillator frequency
Conditions -
Min 11.88
Typ[2] 12
Max 12.12
Unit MHz
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
12.15 f (MHz) 12.05 VDD = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 2.0 V
002aae987
11.95
11.85 -40
-15
10
35
60 85 temperature (C)
Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for 2.7 V VDD 3.6 V and Tamb = -40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 21. Internal RC oscillator frequency f versus temperature Table 14. fosc Dynamic characteristics: Watchdog oscillator Conditions DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register
[1] [2] [3] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. The typical frequency spread over processing and temperature (Tamb = -40 C to +85 C) is 40 %. See the LPC13xx user manual.
[2][3]
Symbol Parameter internal oscillator frequency
Min -
Typ[1] 7.8 1700
Max -
Unit kHz kHz
[2][3]
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10.4 I/O pins
Table 15. Dynamic characteristics: I/O pins[1] Tamb = -40 C to +85 C; 3.0 V VDD 3.6 V. Symbol tr tf
[1]
Parameter rise time fall time
Conditions pin configured as output pin configured as output
Min 3.0 2.5
Typ -
Max 5.0 5.0
Unit ns ns
Applies to standard port pins and RESET pin.
10.5 I2C-bus
Table 16. Dynamic characteristic: I2C-bus pins[1] Tamb = -40 C to +85 C.[2] Symbol fSCL Parameter SCL clock frequency Conditions Standard-mode Fast-mode Fast-mode Plus tf fall time
[4][5][6][7]
Min 0 0 0 -
Max 100 400 1 300
Unit kHz kHz MHz ns
of both SDA and SCL signals Standard-mode Fast-mode Fast-mode Plus
20 + 0.1 x Cb 4.7 1.3 0.5 4.0 0.6 0.26 0 0 0 250 100 50
300 120 -
ns ns s s s s s s s s s ns ns ns
tLOW
LOW period of the SCL clock
Standard-mode Fast-mode Fast-mode Plus Standard-mode Fast-mode Fast-mode Plus
[3][4][8]
tHIGH
HIGH period of the SCL clock
tHD;DAT
data hold time
Standard-mode Fast-mode Fast-mode Plus
tSU;DAT
data set-up time
[9][10]
Standard-mode Fast-mode Fast-mode Plus
[1] [2] [3] [4] [5] [6]
See the I2C-bus specification UM10204 for details. Parameters are valid over operating temperature range unless otherwise specified. tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing.
[7]
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[8]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge.
[9]
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
tf SDA 70 % 30 % tf 70 % 30 % 70 % 30 % tHD;DAT
tSU;DAT
tVD;DAT tHIGH
SCL
70 % 30 %
70 % 30 % tLOW
70 % 30 %
S
1 / fSCL
002aaf425
Fig 22. I2C-bus pins clock timing
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10.6 SSP interface
Table 17. Symbol SSP master Tcy(clk) tDS clock cycle time data set-up time when only receiving when only transmitting in SPI mode; 2.4 V VDD 3.6 V 2.0 V VDD < 2.4 V tDH tv(Q) th(Q) SSP slave Tcy(PCLK) tDS tDH tv(Q) th(Q)
[1]
[2] [2] [2] [2] [1] [1] [2]
Dynamic characteristics: SSP pins in SPI mode Parameter Conditions Min 40 27.8 15 20 0 0 13.9 in SPI mode in SPI mode in SPI mode in SPI mode
[3][4] [3][4] [3][4] [3][4]
Max 10 3 x Tcy(PCLK) + 11 2 x Tcy(PCLK) + 5
Unit ns ns ns ns ns ns ns ns ns ns ns ns
data hold time data output valid time data output hold time PCLK cycle time data set-up time data hold time data output valid time data output hold time
in SPI mode in SPI mode in SPI mode
0 3 x Tcy(PCLK) + 4 -
Tcy(clk) = (SSPCLKDIV x (1 + SCR) x CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). Tamb = -40 C to +85 C. Tcy(clk) = 12 x Tcy(PCLK). Tamb = 25 C; VDD = 3.3 V.
[2] [3] [4]
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Tcy(clk)
tclk(H)
tclk(L)
SCK (CPOL = 0)
SCK (CPOL = 1) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID CPHA = 1 th(Q)
tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID
th(Q)
CPHA = 0
002aae829
Fig 23. SSP master timing in SPI mode
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Tcy(clk)
tclk(H)
tclk(L)
SCK (CPOL = 0)
SCK (CPOL = 1) tDS MOSI DATA VALID tv(Q) MISO DATA VALID DATA VALID tDH DATA VALID th(Q) CPHA = 1
tDS MOSI DATA VALID tv(Q) MISO DATA VALID
tDH
DATA VALID th(Q) DATA VALID CPHA = 0
002aae830
Fig 24. SSP slave timing in SPI mode
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10.7 USB interface (LPC1342/43 only)
Table 18. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD, unless otherwise specified. Symbol tr tf tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise and fall time matching output signal crossover voltage source SE0 interval of EOP source jitter for differential transition to SE0 transition receiver jitter to next transition receiver jitter for paired transitions EOP width at receiver 10 % to 90 % must reject as EOP; see Figure 25 must accept as EOP; see Figure 25
[1]
Conditions 10 % to 90 % 10 % to 90 % tr / tf
Min 8.5 7.7 1.3
Typ -
Max 13.8 13.7 109 2.0 175 +5 +18.5 +9 -
Unit ns ns % V ns ns ns ns ns
see Figure 25 see Figure 25
160 -2 -18.5 -9 40
tEOPR2
EOP width at receiver
[1]
82
-
-
ns
[1]
Characterized but not implemented as production test. Guaranteed by design.
TPERIOD crossover point differential data lines
crossover point extended
source EOP width: tFEOPT differential data to SE0/EOP skew n x TPERIOD + tFDEOP
receiver EOP width: tEOPR1, tEOPR2
002aab561
Fig 25. Differential data-to-EOP transition skew and EOP width
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11. Application information
11.1 Suggested USB interface solutions (LPC1342/43 only)
VDD
USB_CONNECT
LPC134x
soft-connect switch
R1 1.5 k
USB_VBUS USB_DP RS = 33 USB_DM VSS
002aae608 RS = 33
USB-B connector
Fig 26. LPC1342/43 USB interface on a self-powered device
VDD
LPC134x
USB_VBUS USB_DP RS = 33 USB_DM RS = 33 VSS
R1 1.5 k
USB-B connector
002aae609
Fig 27. LPC1342/43 USB interface on a bus-powered device
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed.
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LPC1xxx
XTALIN
Ci 100 pF Cg
002aae788
Fig 28. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 28), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 29 and in Table 19 and Table 20. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 29 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer.
LPC1xxx
L
XTALIN
XTALOUT =
XTAL CL CP
RS CX1 CX2
002aaf424
Fig 29. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation
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Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Crystal load capacitance CL 10 pF 20 pF 30 pF Maximum crystal series resistance RS < 300 < 300 < 300 < 300 < 200 < 100 < 160 < 60 < 80 External load capacitors CX1, CX2 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF
Table 19.
Fundamental oscillation frequency FOSC 1 MHz - 5 MHz
5 MHz - 10 MHz
10 pF 20 pF 30 pF
10 MHz - 15 MHz 15 MHz - 20 MHz Table 20.
10 pF 20 pF 10 pF
Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Crystal load capacitance CL 10 pF 20 pF 10 pF 20 pF Maximum crystal series resistance RS < 180 < 100 < 160 < 80 External load capacitors CX1, CX2 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF 39 pF, 39 pF
Fundamental oscillation frequency FOSC 15 MHz - 20 MHz 20 MHz - 25 MHz
11.3 XTAL Printed-Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout.
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11.4 Standard I/O pad configuration
Figure 30 shows the possible pin modes for standard I/O pins with analog input function:
* * * * *
Digital output driver Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Analog input
VDD
output enable pin configured as digital output driver output
ESD PIN ESD
VDD weak pull-up pull-up enable repeater mode enable pull-down enable weak pull-down
VSS
pin configured as digital input
data input
select analog input pin configured as analog input analog input
002aaf304
Fig 30. Standard I/O pad configuration
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11.5 Reset pad configuration
VDD VDD VDD
Rpu
ESD
reset
20 ns RC GLITCH FILTER
PIN
ESD
VSS
002aaf274
Fig 31. Reset pad configuration
11.6 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 8:
* The ADC input trace must be short and as close as possible to the LPC1311/13/42/43
chip.
* The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
* Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
* To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
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12. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 32. Package outline SOT313-2 (LQFP48)
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HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm
D
B
A
terminal 1 index area
E
A
A1 c
detail X
e1 e 9 L 8 17 e b 16 v w CAB C y1 C
C y
Eh
e2
1
33
24 X
terminal 1 index area
32 Dh
25
0 Dimensions Unit mm A(1) A1 b c 0.2 D(1) 7.1 7.0 6.9 Dh 4.85 4.70 4.55 E(1) 7.1 7.0 6.9 Eh e
2.5 scale e1 e2 L
5 mm
v 0.1
w
y
y1 0.1
max 1.00 0.05 0.35 nom 0.85 0.02 0.28 min 0.80 0.00 0.23
0.75 4.85 4.70 0.65 4.55 4.55 0.60 0.45 4.55
0.05 0.08
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC JEDEC JEITA --European projection
hvqfn33_po
Issue date 09-03-17 09-03-23
Fig 33. Package outline (HVQFN33)
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13. Abbreviations
Table 21. Acronym A/D ADC AHB AMBA APB BOD EOP ETM FIFO GPIO HID I/O LSB MSC PHY PLL SE0 SPI SSI SSP SoF TCM TTL UART USB Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection End Of Packet Embedded Trace Macrocell First-In, First-Out General Purpose Input/Output Human Interface Device Input/Output Least Significant Bit Mass Storage Class Physical Layer Phase-Locked Loop Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Start-of-Frame Tightly-Coupled Memory Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus
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14. Revision history
Table 22. Revision history Release date 20100810 Data sheet status Product data sheet Change notice Supersedes LPC1311_13_42_43 v.2 Document ID LPC1311_13_42_43 v.3 Modifications:
* * * * * * * * * *
VESD limit changed to -6500 V (min) /+6500 V (max) in Table 6. Reset state of pins and start logic functionality added in Table 3 to Table 4. Section 7.18.1 added. Table "Power consumption in Deep-sleep mode for individual analog blocks" removed. Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the only analog blocks allowed to remain running in Deep-sleep mode (Section 7.17.5.2). VDD range changed to 3.0 VDD 3.6 V in Table 15. Tcy(CLK) conditions updated in Table 17. Size of GPIO registers updated in Figure 6. Editorial updates. Template updated. Product data sheet Product data sheet LPC1311_13_42_43 v.1 -
LPC1311_13_42_43 v.2 LPC1311_13_42_43 v.1
20100506 20091211
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NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2010. All rights reserved.
15.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 3 -- 10 August 2010
59 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 -- 10 August 2010
60 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
17. Contents
1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . 16 Architectural overview . . . . . . . . . . . . . . . . . . 16 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 16 On-chip flash program memory . . . . . . . . . . . 16 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18 7.7 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 18 7.8 Fast general purpose parallel I/O . . . . . . . . . . 18 7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 USB interface (LPC1342/43 only) . . . . . . . . . 19 7.9.1 Full-speed USB device controller . . . . . . . . . . 19 7.9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11 SSP serial I/O controller . . . . . . . . . . . . . . . . . 20 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12 I2C-bus serial I/O controller . . . . . . . . . . . . . . 20 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.15 System tick timer . . . . . . . . . . . . . . . . . . . . . . 22 7.16 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 22 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 Clocking and power control . . . . . . . . . . . . . . 22 7.17.1 Integrated oscillators . . . . . . . . . . . . . . . . . . . 22 7.17.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 24 7.17.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 24 7.17.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 24 7.17.2 System PLL and USB PLL . . . . . . . . . . . . . . . 24 7.17.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.17.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 24 Power control . . . . . . . . . . . . . . . . . . . . . . . . . Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . Deep power-down mode . . . . . . . . . . . . . . . . System control . . . . . . . . . . . . . . . . . . . . . . . . Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Brownout detection . . . . . . . . . . . . . . . . . . . . Code security (Code Read Protection - CRP) . . . . . . . . . . . 7.18.5 Boot loader. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18.6 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 7.18.7 AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18.8 External interrupt inputs . . . . . . . . . . . . . . . . . 7.18.9 Memory mapping control . . . . . . . . . . . . . . . . 7.19 Emulation and debugging . . . . . . . . . . . . . . . 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 9 Static characteristics . . . . . . . . . . . . . . . . . . . 9.1 BOD static characteristics . . . . . . . . . . . . . . . 9.2 Power consumption . . . . . . . . . . . . . . . . . . . 9.3 Peripheral power consumption . . . . . . . . . . . 9.4 Electrical pin characteristics. . . . . . . . . . . . . . 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 USB interface (LPC1342/43 only) . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . 11.1 Suggested USB interface solutions (LPC1342/43 only) . . . . . . . . . . . . . . . . . . . . . 11.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 11.4 Standard I/O pad configuration . . . . . . . . . . . 11.5 Reset pad configuration . . . . . . . . . . . . . . . . . 11.6 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.17.5 7.17.5.1 7.17.5.2 7.17.5.3 7.18 7.18.1 7.18.2 7.18.3 7.18.4 25 25 25 25 25 25 26 26 26 27 27 27 27 27 27 28 29 34 34 37 38 42 42 42 43 44 44 46 49 50 50 50 52 53 54 54 55 57 58 59 59 59
continued >>
LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 -- 10 August 2010
61 of 62
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
59 60 60 61
15.3 15.4 16 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 August 2010 Document identifier: LPC1311_13_42_43

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